1. Field of the Invention
The present invention relates generally to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device with an improved contact plug suitable for highly integrated semiconductor devices.
2. Description of the Related Art
As is well known, it is essential to reduce contact resistance in a semiconductor IC circuit line width to below 0.16 μm.
According to recent methods of forming a silicon contact plugs, a contact hole is formed and then, polycrystalline silicon is deposited therein. A planation process is performed by using chemical mechanical polishing (CMP).
Generally, it is desirable to apply silicon epitaxial growth (SEG) during the manufacturing process of semiconductor devices since it is possible to reduce cell size, simplify the manufacturing process and improve electrical properties by SEG.
Therefore, a plug using SEG can solve the problems of gap-fill and increases of contact resistance, due to reduced cell size.
It is also possible to simplify the manufacturing process since CMP and silicon recess etch are not required to be performed for plug isolation.
However, there are several problems in applying SEG during plug formation.
First, there is the problem of selectively of the pattern material, that is, a material forming a window to grow the SEG.
The surface of the nitride layer is exposed when a self-aligned contact (SAC) etch is applied to the cell activation regions. The SEG has a different facet generation due to selectivity and thermal stress, and according to the pattern material.
Generally, in a low pressure chemical vapor deposition (LPCVD) process, nitride materials have difficulty in achieving selectivity at temperatures below 850° C., compared with oxide materials.
Therefore, the growth speed is lowered in order to have selectivity, thereby increasing thermal growth on the surface of the device.
The conventional method for manufacturing a semiconductor device will be described in more detail with reference to the accompanying drawings.
FIGS. 1 to 4 are cross sectional views for showing a conventional method of manufacturing a semiconductor device.
Referring to FIG. 1, a gate electrode 3 is formed on a silicon substrate 1 and then, a sidewall spacer 5 is formed on the side of the gate electrode 3.
Although it is not shown in the drawings, impurity junction regions are formed by implanting impurities in the silicon substrate 1 on the lower parts of both sides of the sidewall spacer 5.
Subsequently, an interlayer insulating layer 7 is deposited on the silicon substrate 1 including over the gate electrode 3 and the sidewall spacer 5.
Referring to FIG. 2, the interlayer insulating layer 7 is subjected to a mask formation process using lithography and patterning processes to form a plug contact hole 9 exposing the impurity junction regions (not shown).
Referring to FIG. 3, an amorphous silicon layer 11 is deposited to fill the plug contact hole 9 on the upper part of the interlayer insulating layer 7 including the plug contact hole 9.
Then, a CMP or silicon recess etch process is performed on the amorphous silicon layer 11, thereby forming a contact plug 11a in the plug contact hole 9, to electrically contact the impurity junction regions (not shown).
However, the conventional method has several problems in forming the contact hole and the contact plug having a high aspect ratio, and especially when the circuit line width is below 0.16 μm.
First, according to the conventional method, in order to form a plug with silicon, CMP or a silicon recess etch is required to be performed on the oxide layer, followed by contact hole formation, amorphous silicon deposition and plug isolation. Therefore, a problem arises in higher production costs.
It is also difficult to prevent generation of natural oxide layers on the interface of the cell and plug since in-situ cleaning is not performed in a tube type LPCVD. Therefore, contact resistance of the polycrystalline silicon plug is increased by three times more than that of selective epitaxial growth (SEG).
Also, there is a problem of gap-fill in silicon deposition due to reduced contact hole size and increased aspect ratio.
Moreover, compared with a SEG (epitaxial layer), diffusion of phosphorus is increased in the high doped amorphous or polycrystalline silicon, thereby deteriorating the device properties.
Although it is not shown in the drawings, another alternative embodiment of the conventional method will be described in the following description.
According to the alternative embodiment, an interlayer insulating layer (not shown) is first deposited using a nitride material on a silicon substrate (not shown) having a gate electrode and impurity junction regions.
Then, a contact hole (not shown) is formed to expose the impurity junction regions (not shown) by selectively patterning the interlayer insulating layer (not shown).
Subsequently, a SEG plug is formed in the contact hole (not shown), maintaining selectivity with the interlayer insulating layer (not shown) pattern of nitride material.
This alternative embodiment has the advantages of reducing contact resistance and simplifying the plug formation process by using selective epitaxial growth.
However, when a LPCVD method is applied to the conventional method, HCl is increased in order to maintain selectivity on the surface of the nitride layer, thereby lowering the growth speed of SEG.
The nitride material has a thermal coefficient of expansion (TCE) higher than that of silicon, thereby generating defects of SEG due to the difference in thermal expansion.
It is difficult to have a processing margin on the surface of the nitride layer during a process of applying a UVH-CVD method.
Moreover, in the nitride layer pattern, regions having selectivity are decreased by ten times compared to in the oxide layer, at temperatures below 900° C.
When a SEG is formed, the nitride pattern generates defects at a higher temperature than that of the oxide layer.
It is also difficult to maintain selectivity of the nitride layer in-situ. Even if the selectivity is maintained, it is impossible to prevent a decrease in growth speed.
As a result, the thermal budget of SEG is increased and the device properties are deteriorated.
Moreover, overgrowth of SEG may be generated according to the density and shape of the cell pattern, thereby generating problems during CMP on the interlayer insulating layer.